//-----------------------------------------------------------------------------
//
// Title       : memoria_tb
// Design      : ACA2008
// Author      : KUI LI
// Company     : home
//
//-----------------------------------------------------------------------------
//
// File        : memoria_TB.v
// Generated   : Sun Jun 29 06:16:26 2008
// From        : c:\My_Designs\aca2008\ACA2008\src\TestBench\memoria_TB_settings.txt
// By          : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`timescale 1ps / 1ps
module memoria_tb;


//Internal signals declarations:
reg clk;
reg reset;
reg [63:0]Bus_Data_O;
reg [63:0]Bus_Data_I;
reg [15:0]Bus_Adr;
reg [2:0]Bus_Ctl;
reg Bus_ACK;
reg Bus_Gnt;
wire MemSys_ACK;
wire [63:0]Mem_Data_I;



// Unit Under Test port map
	memoria UUT (
		.clk(clk),
		.reset(reset),
		.Bus_Data_O(Bus_Data_O),
		.Bus_Data_I(Bus_Data_I),
		.Bus_Adr(Bus_Adr),
		.Bus_Ctl(Bus_Ctl),
		.Bus_ACK(Bus_ACK),
		.Bus_Gnt(Bus_Gnt),
		.MemSys_ACK(MemSys_ACK),
		.Mem_Data_I(Mem_Data_I));

initial	begin
  $monitor($realtime,,"ps %h %h %h %h %h %h %h %h %h %h ",clk,reset,Bus_Data_O,Bus_Data_I,Bus_Adr,Bus_Ctl,Bus_ACK,Bus_Gnt,MemSys_ACK,Mem_Data_I);
  clk = 0;
  reset = 0;
  Bus_Data_O= 0;
  Bus_Adr	= 0;
  Bus_Ctl	= 0;
  Bus_ACK	= 0;
  Bus_Gnt	= 0;
  
  // Escriure dades
  #5 Bus_Gnt = 1;
  Bus_Ctl = 3'b010;
  Bus_Adr = 22'd45;
  Bus_Data_O = 64'h8888888888888888;
  #20 Bus_Gnt = 0;

  // Llegir dades

  #5 Bus_Gnt = 1;
  Bus_Ctl = 3'b000;
  Bus_Adr = 22'd45;
  Bus_Data_O = 0;
  #20 Bus_Gnt = 0;
  
  #10 $finish;
end

always begin
 #5 clk = !clk;
end
endmodule
